The invention relates to semiconductor memory devices useful, e.g., as electrically alterable memory elements. In particular, the invention relates to an improved field effect memory transistor in which parasitic transistor action along the gate edges is controlled.
MNOS (metal-nitride-oxide-semiconductor) and SNOS (polySilicon-nitride-oxide-semiconductor) devices are derived from the MIS (metal-insulator-semiconductor) structure. Such devices have a silicon nitride layer interposed between the silicon dioxide gate insulation layer and the gate electrode, thus providing a dual layer gate insulator. The silicon dioxide is relatively susceptible to charge carrier tunneling and has a low charge trapping ability, while the silicon nitride has a relatively high charge trapping ability. As is well-known by those skilled in the art, the memory capabilities of the MNOS and SNOS structures are utilized by forming the silicon dioxide layer sufficiently thin to permit charge tunneling through the silicon dioxide layer. Then, upon application of a suitable gate voltage across the gate electrode and the semiconductor substrate, charge carriers tunnel from the substrate through the silicon dioxide layer or vice versa and are trapped in the silicon nitride proximate the silicon dioxide-silicon nitride interface. The trapped charge remains after the voltage has been removed and is reflected by a charge of opposite polarity in the surface region of the substrate.
The reflected substrate charge alters the threshold conduction voltage of the device. The presence or absence of such a charge can thus be used to "write" or "erase" the device to a desired binary state. That is, the threshold voltage of the device can be changed to either a high value or a low value corresponding to a binary bit of "1" or "0" (or vice versa). This stored bit may then be read by applying a gate voltage which is between the high and the low threshold voltages. If the device turns "on" and conducts, a bit of one value is read or, if the device does not turn on, a bit of the other value is read.
Memory devices using the silicon nitride-silicon oxide gate insulation structure are particularly desirable for their nonvolatility. That is, they will hold a trapped charge and resulting binary state for a long time. Consequently, it is not necessary to continually refresh each device or provide special circuitry or other means to compensate for a power breakdown.
Devices, such as memory MNOSFETs or SNOSFETs, which employ relatively thin gate insulation in a well surrounded by thick insulation, may be subject to parasitic transistor action along the edges of the gate. Referring to FIG. 1, there is shown a cross-sectional view of such a memory MNOSFET device 15. The device 15 comprises a substrate 11 of one conductivity type; source 12 and drain 13 of the opposite conductivity type formed in the substrate; thick "field" oxide layer 16 on the substrate for electrically isolating the device; a gate structure 17 comprising thin, charge-tunneling memory oxide layer 18 formed within the field oxide 16, charge-trapping silicon nitride layer 19 and gate electrode 21; and source and drain electrodes 22 and 23, respectively. Parasitic transistor conduction occurs along the opposite edges 24 and 26 (see FIGS. 2 and 3) of the gate structure parallel to the channel as the result of the fringing field which occurs upon application of a polarizing gate voltage across the gate structure, i.e., between gate electrode 21 and substrate 11. The parasitic transistor action results from sloping oxide transition regions which are formed in the field oxide 16 along the edges 24 and 26 of the gate during fabrication of the device 15.
Referring now to FIGS. 2 and 3, there are shown, respectively, a plan view, and a perspective view along a section taken parallel to the channel of a semiconductor chip which is at an intermediate stage of fabrication of the prior art memory MNOSFET device 15 (FIG. 1) or the memory MNOSFET device 50 (FIG. 5) of the present invention. In pertinent part, the fabrication typically involves initially forming the field oxide layer 16 on substrate 11, and etching openings in the substrate and diffusing impurities through the openings into the substrate to form the source 12 and drain 13.
Then, in forming the gate structure 17 (FIG. 1) a mask (not shown) is applied to the field oxide 16 and a well 29 is etched in the field oxide to the surface of the substrate 11. As shown in FIG. 3, etching undercuts the field oxide 16 beneath the mask so that the walls 31, 32, 33, 34 of the field oxide well 29 slope outwardly, away from the base region of the well formed between the walls in the direction from the interface region 36 (formed by the inner surfaces of the substrate 11 and the field oxide) to outer surface 37 of the field oxide 16. The sloping walls remain after subsequent growth/deposit in the well of the relatively thin gate oxide(s) (which forms memory oxide 18 in the well and thereby forms base 35 of the well) and after completion of the device 15.
Because of the sloping side walls 31, 32, 33, 34, the transition from thin memory gate oxide 18 (typically 10 to 60 Angstroms) to thick field oxide 16 (typically 10,000 to 20,000 Angstroms) is sloped or gradual rather than abrupt. That is, regions of transition from the thin memory oxide to the thick field oxide are formed along each side of the gate. However, gate parasitic device action is a concern only along the sides of the gate which extend between the source and drain. Accordingly, our discussion here is limited to transition regions 27 and 28 formed beneath walls 31 and 33 along gate sides 24 and 26.
As discussed previously, the memory oxide 18 is formed sufficiently thin to permit charge carrier tunneling between the substrate and the gate structure and thereby impart alterable threshold characteristics to the structure. The field oxide 16 is sufficiently thick to preclude tunneling and any resulting alterable threshold characteristics and, in fact, is sufficiently thick to preclude any inversion of the underlying substrate and creation of a conduction channel therein by normal applied fields. However, each of the transition regions 27 and 28 has a portion (arbitrarily shown as portions 27a and 28a in FIG. 3) which is approximately parallel to the edges 24 and 26 and is thin enough to permit transistor action, but is too thick to permit tunneling and the resulting alterable threshold characteristics. In the presence of a suitable electric field such as the fringing field associated with gate voltages, this non-alterable, non-memory "parasitic" transistor action produces conduction channels in the substrate 11 beneath transition regions 27a and 28a. The channels extend proximate to and approximately parallel to the edges 24 and 26 of the gate between the source 12 and the drain 13.
Referring to the plan view of FIG. 2, the current flow along the channels associated with the parasitic transistors P.sub.1 and P.sub.2 is represented by arrows. Because the MNOS device 15 is shown here prior to completion, it is inoperative. Parasitic transistors P.sub.1 and P.sub.2 of course would not be present in the inoperative device, but are shown in the plan view to better demonstrate their physical location and operation in the completed device 15 of FIG. 1.
The effect of the parasitic FETs P.sub.1 and P.sub.2 is shown in FIG. 4. A typical P-channel MNOSFET might be set to a low threshold voltage of approximately -3 volts by application of a polarizing gate voltage of +20 to +30 volts for 100 milliseconds. This is shown by the erase or "0" state curve 38 in FIG. 4. Likewise, by applying -20 volts to -30 volts for 100 milliseconds, a threshold voltage of about -6 volts might be expected for the written or "1" state curve 39. However, the parasitic transistors P.sub.1 and P.sub.2 typically have a low threshold voltage, perhaps -3 volts in the high threshold, "1" state. This is indicated by the dotted tail 41 of the "1" state curve 39. The parasitic device may then be turned on and conducting at 3-4 .mu.A across all or a substantial portion of the window between the "0" and "1" threshold voltages. Any circuit employing the device 15 must use sensing circuitry which is insensitive to such parasitic currents.
An approach for controlling this gate parasitic transistor action is taught in the aforementioned U.S. application Ser. No. 847,206, entitled MNOS DEVICE HAVING CONTROLLED GATE PARASITIC ACTION, filed Oct. 31, 1977 in the name of W. Spence and assigned to the assignee of the present application. Here, the gate memory oxide has sections which project outwardly from the sides of the gate. The perimeter of each projecting section defines elongated transition regions which increase the channel length of the parasitic device and thereby decrease the parasitic drain current. This approach is very efficient in controlling gate parasitic device action without additional process steps, although the projections probably decrease the density achievable using the transistor design.
Another approach is taught by P. J. Krick in "The Implanted Stepped-Oxide MNOS FET", IEEE Transactions on Electron Devices, February, 1973, page 62. There, parasitic FET action is eliminated in N-channel devices and the window widened by implanting a P-type substrate with boron (P-type) ions. This implanting is done at the edge of the memory oxide adjacent to the channel using the gate metalization and field oxide as the implanting mask. The reported purpose of the implantation is to increase the threshold voltage of the region adjacent to the gate metal beyond the high-state threshold voltage of the MNOS FET and thereby prevent inversion of the substrate by fringing fields from the gate electrode. The Krick article does not recognize that the oxide transition regions themselves can be used to control the depth of a blanket implant and thereby to eliminate the problem of parasitic gate action, and without deleteriously affecting the operation of the device.
An approach for controlling parasitic inversion beneath the thick field oxide associated with a semiconductor device is taught in U.S. Pat. No. 3,860,454 issued Jan. 14, 1975, to DeWitt and Johnson. This patent utilizes the difference in thicknesses of the gate and field regions to implant a layer of impurities at different depths in the device. The layer is buried just under the oxide of the field region and deep within the substrate in the gate region. The implanted impurities, which are of the same conductivity as the background doping of the substrate, prevent parasitic inversion and the resulting conduction in the field regions of the substrate without deleteriously affecting the gate region. This patent is not directed to the problem of lateral parasitic transistor action, does not recognize the cause of the problem and, like the Krick article, does not recognize that the cause of the problem may in fact be used in the solution.